Design And Reuse

CAST Simplifies RISC-V Embedded Processor IP Adoption with New Catalyst Program

Sourced from Beyond Semiconductor and Fraunhofer IPMS, the Catalyst RISC-V processor cores are available now for ASICs and FPGAs. For product briefs, evaluation information, and licensing details, ...
Design And Reuse

Ceva Introduces Wi-Fi 7 1x1 Client IP to Power Smarter, More Responsive AI-Enabled IoT Devices and Emerging Physical AI Systems

Already adopted by leading semiconductor companies, Ceva-Waves Wi-Fi 1x1 7 client IP leverages IEEE 802.11be to deliver the performance, reliability and power efficiency required for compact, ...
Design And Reuse

Weebit Nano delivers record quarterly customer receipts

Quarterly customer receipts represented a record A$7.3 million in Q1 FY26. Other notable cash inflows included A$4.1 million relating to 2024 R&D tax rebate for Weebit’s French subsidiary. R&D ...
Design And Reuse

Menta Brings its Pioneering eFPGA Technology to Embedded World North America 2025

“Embedded World North America is the perfect stage for us to show how eFPGA technology is reshaping the future of chip design,” said Vincent Markus, CEO of Menta. “As system complexity grows and ...
Design And Reuse

Sofics Tapes Out Test Chip on TSMC 4nm Process with Novel ESD IP and Low-Power 1.8V and 3.3V GPIO Solutions

Sofics (www.sofics.com) is a leading independent provider of semiconductor IP for on-chip ESD, I/O and reliability solutions. Sofics IP is integrated in more than 5000 tape outs across CMOS, FinFET, ...
Design And Reuse

Arteris Selected by 2V Systems for IO Chiplet for Data Center

The Arteris highly flexible and silicon-proven network-on-chip (NoC) interconnect IPs are ideal for serving as the data highway in the IO chiplet, meeting the energy and performance requirements for ...
Design And Reuse

Arm Accelerates the Edge AI Revolution with Easy, Low-Cost Access to Armv9 Platforms through Arm Flexible Access

By adding the Armv9 edge AI platform to Arm Flexible Access, we’re offering the smoothest market entry, lowest cost, and fastest innovation path for any company building AI-capable edge devices. This ...
Design And Reuse

Ceva Advancing Real-Time AI with Transformers and Intelligent Quantization

In an earlier collaborative project, Ceva worked with CERN on the trigger system of the Large Hadron Collider (LHC), a sophisticated real-time filtering mechanism that deals with the torrent of ...
Design And Reuse

Ethernet IP Core Leaders – Comprehensive Portfolio from 10M to 10G

With IP cores ranging from 10M to 10G Ethernet PHY and scalable MAC solutions from 10M up to 800G, T2M has built one of the industry’s most versatile and future-ready Ethernet portfolios. This ...
Design And Reuse

NVIDIA partners with TSMC, and the first wafer of the Blackwell chips manufactured in the United States is unveiled.

On Friday, NVIDIA and TSMC unveiled the first Blackwell chip wafer at their factory in Arizona, USA. These wafers will ultimately be used to manufacture Blackwell chips for artificial intelligence.
Design And Reuse

Synopsys Unveils ‘Silicon Bring-Up’ of LPDDR6 IP On TSMC’s Cutting-Edge N2P Node, Reaching Bandwidth Up to a Whopping 86 GB/s

Synopsys has unveiled a massive development in the realm of mobile memory, as it announced the silicon bring-up of its LPDDR6 IP based on TSMC's N2P node. Synopsys LPDDR6 IP Block Manages To Witness ...
Design And Reuse

Andes Showcases Expanding RISC-V Ecosystem and Next-Generation "Cuzco" High-Performance CPU at RISC-V Summit North America 2025

Building on its success in bringing RISC-V to the mainstream, Andes is now extending its leadership into the high-performance domain. Cuzco, first revealed at Hot Chips 2025, introduces a time-based ...